The present invention relates to memory devices generally and, more particularly, to an address counter test mode for a memory device.
When testing a memory device, it is generally necessary to test several different memory array patterns on a RAM device to ensure correct functionality. Each memory array pattern requires a large number of test vectors. Memory testers typically have specialized logic that is used to generate the memory array test patterns automatically, with very little vector memory requirement. General purpose logic testers (e.g., those used for testing dual-port SRAMs or embedded SRAMs) typically do not have the test capability to provide the number of test patterns required. As a result, a large memory on the tester device may be required to test the memory array. By implementing the vectors on the memory of the tester device, long test times may be required (generally caused by the additional time needed to load more than one vector data block to the tester) or expensive vector memory expansion may be required. A pseudo-random address generator is sometimes used to reduce the memory overhead or test time. However, a pseudo-random address generator does not give full coverage of all required memory array addressing sequences.
Conventional approaches to testing memories may include (i) built-in address counters in the memory device being tested allow cycling through all addresses in a linear sequence, (ii) memory testers used to generate array patterns and (iii) additional CT memory that may be added to logic testers to enable larger vector sets without the need to reload vectors during testing, however the additional memory adds expense to the tester device.
The present invention concerns a memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.
A second aspect of the present invention concerns a circuit comprising a memory element, a first gate circuit, and an increment circuit. The memory element may be configured to generate a counter output in response to (i) a clock input and (ii) a first input. The first circuit may be configured to present the first input in response to (i) a control input and (ii) an increment input. The increment circuit may be configured to present the increment input in response to the counter output.
The objects, features and advantages of the present invention include providing a memory array having a built-in address generator that may assert a test mode to generate a number of address sequences for testing the array without a speed penalty and using a minimum of chip real estate.